Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 778

SCC Ethernet Mode
27.21 SCC Ethernet Programming Example
The following is an initialization sequence for the SCC2 in ethernet mode. The CLK1 pin is used for the
ethernet receiver and CLK2 is used for the transmitter.
1. Configure port A to enable TXD2 and RXD2. Set PAPAR[12, 13] and clear PADIR[12, 13] and
PAODR[12,13].
2. Configure port C to enable CTS2 (CLSN) and CD2 (RENA). Clear PCPAR[8.9] and PCDIR[8,9]
and set PCSO[8,9].
3. Do not enable the RTS2 (TENA) pin yet because it is still functioning as RTS and transmission on
the LAN could begin accidentally.
4. Configure port A to enable the CLK1 and CLK2 pins. Set PAPAR[6, 7] and clear PADIR[6, 7].
5. Connect CLK1 and CLK2 to SCC2 using the serial interface. Set SICR[R2CS] to 0b101 and
SICR[T2CS] to 0b100.
6. Connect the SCC2 to the NMSI and clear SICR[SC2].
7. Initialize the SDMA configuration register (SDCR) to 0x00000040.
8. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and TxBD in the
dual-port RAM. Assuming one RxBD at the beginning of the dual-port RAM and one TxBD
following that RxBD, write RBASE with 0x0000 and TBASE with 0x0008.
9. Program the CPCR to execute an
10. Write RFCR and TFCR with 0x10 for normal operation.
11. Write MRBLR with the maximum number of bytes per receive buffer. Here, assume 1520 bytes,
so MRBLR = 0x05F0. In this example, the user wants to receive an entire frame into one buffer,
so MRBLR is the first value larger than 1518 evenly divisible by four.
12. Write C_PRES with 0xFFFF_FFFF to comply with 32-bit CCITT-CRC.
13. Write C_MASK with 0xDEBB_20E3 to comply with 32-bit CCITT-CRC.
14. Clear CRCEC, ALEC, and DISFC for clarity.
15. Write PAD with 0x8888 for the PAD value.
16. Write RET_LIM with 0x000F.
17. Write MFLR with 0x05EE to make the maximum frame size 1518 bytes.
18. Write MINFLR with 0x0040 to make the minimum frame size 64 bytes.
19. Write MAXD1 and MAXD2 with 0x05F0 to make the maximum DMA count 1520 bytes.
20. Clear GADDR1–GADDR4. The group hash table is not used.
21. Write PADDR1_H with 0x0380, PADDR1_M with 0x12E0, and PADDR1_L with 0x5634 to
configure the physical address 0x8003_E012_3456.
22. Clear P_PER. It is not used.
23. Clear IADDR1–IADDR4. The individual hash table is not used.
24. Clear TADDR_H, TADDR_M, and TADDR_L for clarity.
25. Initialize the RxBD and assume the Rx data buffer is at 0x0000_1000 in main memory. Write
0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and
0x0000_1000 to RxBD[Buffer Pointer].
27-22
INIT RX AND TX PARAMETERS
MPC885 PowerQUICC Family Reference Manual, Rev. 2
command for this channel.
Freescale Semiconductor