Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 564

Communications Processor Module and CPM Timers
17.2.4.1 Timer Reference Registers (TRR1–TRR4)
Each timer reference register (TRR1–TRR4), shown in
value. The reference value is not reached until TCNx increments to equal the timeout reference value.
These registers are affected by HRESET and SRESET.
0
Field
Reset
R/W
Addr
17.2.4.2 Timer Capture Registers (TCR1–TCR4)
Each timer capture register (TCR1–TCR4), shown in
according to TMRx[CE].These registers are affected by HRESET and SRESET.
0
Field
Reset
R/W
Addr
17.2.4.3 Timer Counter Registers (TCN1–TCN4)
Each timer counter register (TCN1–TCN4), shown in
TCN1–TCN4 yields the current value of the timer, but does not affect the counting operation. A write cycle
to TCN1–TCN4 sets the register to the written value, thus causing its corresponding prescaler, TMRx[PS],
to be reset.
0
Field
Reset
R/W
Addr
Note that the counter registers may not be updated correctly if a write is made while the timer is not
running. Use TRRx to define the preferred count value.These registers are affected by HRESET and
SRESET.
17-10
Timeout Reference Value
0x994 (TRR1), 0x996 (TRR2), 0x9A4 (TRR3), 0x9A6 (TRR4)
Figure 17-7. Timer Reference Registers (TRR1–TRR4)
Latched Counter Value
0x998 (TCR1), 0x99A (TCR2), 0x9A8 (TCR3), 0x9AA (TCR4)
Figure 17-8. Timer Capture Registers (TCR1–TCR4)
0x99C (TCN1), 0x99E (TCN2), 0x9AC (TCN3), 0x9AE (TCN4)
Figure 17-9. Timer Counter Registers (TCN1–TCN4)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Figure 17-7, contains the timeout's reference
0xFFFF
R/W
Figure 17-8, is used to latch the value of the counter
0
R/W
Figure 17-9, is an up-counter. A read cycle to
Up Counter
0
R/W
15
15
15
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