Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 397

CLKOUT
BR
BG
BB
A[0:27]
A[28:29]
A[30:31]
R/W
TSIZ[0:1]
BURST
TS
BDIP
Data
TA
BI
13.4.5 Alignment and Data Packing on Transfers
The MPC885 external bus supports only natural address alignment:
• Byte access can have any address alignment
• Half-word access must have A[31] = 0b0
• Word access must have A[30:31] = 0b00
• For burst accesses A[30:31] = 0b00
Freescale Semiconductor
n n+1 Mod 4
00
Figure 13-18. Burst-Inhibit Cycle: 32-Bit Port Size
MPC885 PowerQUICC Family Reference Manual, Rev. 2
n+2 Mod 4 n+3 Mod 4
External Bus Interface
13-23