Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 234

Instruction and Data Caches
cases when the instruction is inside a predicted path. The MPC885 instruction cache evaluates fetch
requests to see if they are inside a predicted path. If a hit is detected, the requested instruction is delivered
to the core. However, if it is a cache miss, the miss sequence is not initiated in most cases until the core
finishes the branch evaluation.
7.5.4 Fetching Instructions from Caching-Inhibited Regions
The caching-inhibited/caching-allowed attributes of a memory region are programmed in the memory
management unit (MMU). To improve performance when fetching instructions from caching-inhibited
regions, the MPC885 loads the burst buffer with a full 4-word block. Instructions that are stored in the burst
buffer and originate from a cache-inhibited region, can be sent to the instruction sequencer, at most, once
before being refetched.
If an instruction fetch from a caching-inhibited region results in a cache hit, the instruction is delivered to
the instruction sequencer in the core from the cache and not from memory. However, it is considered a
programming error if an instruction fetch from a caching-inhibited region results in a cache hit. Software
must ensure that instructions from a caching-inhibited region have not been previously loaded into the
cache, or, if so, those blocks have been flushed from the cache. See
Memory Region Attributes,"
It is also considered a programming error to perform load-and-lock cache block operations from zero wait
state devices that are located on the internal bus. The MPC885 considers these devices as caching-inhibited
memory regions. If a load-and-lock cache block operation is performed from such a device, the instruction
is not guaranteed to be fetched from the instruction cache; in most cases, the instruction is fetched from
the device, regardless of whether it is in the instruction cache.
7.5.5 Updating Code and Memory Region Attributes
The instruction cache does not perform snooping, so if a processor modifies a memory location that may
be contained in the instruction cache, software must ensure that such memory updates are visible to the
instruction fetching mechanism. Also, whenever the memory/cache attributes of any memory region are
changed, it is critical that the cache contents reflect the new attributes. Therefore, when updating code or
changing memory region attributes (in the MMU) the user must perform the following steps:
1. Update code/change memory region attributes.
2. Execute a sync instruction to ensure the update/change operation finished.
3. Unlock all locked cache blocks containing code that was updated.
4. Invalidate all cache blocks containing code that was updated.
5. Execute an isync instruction.
7.6 Data Cache Operation
When the data MMU is enabled (MSR[DR] = 1), the data cache operates as defined by the memory/cache
access attributes. When the data MMU is disabled (MSR[DR] = 0), the data cache operates as defined by
the default data memory access attributes. The default state of the write-through/write-back attribute is
determined by MD_CTR[WTDEF]; the caching-inhibited/caching-allowed attribute is determined by
7-22
for more information.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Section 7.5.5, "Updating Code and
Freescale Semiconductor