Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 453

Bits Name
29 TRLX Timing relaxed (GPCM only)
0 Timing is not relaxed.
1 In addition to the timing parameters programmed in other OR x fields, timing is further relaxed.
See the effect of TRLX in
30 EHTR Extended hold time on read. (GPCM only)
0 Timing is defined by the memory controller.
1 After a read from the current bank, an additional clock cycle is inserted before the memory
controller responds to a write or read to another bank.
31 — Reserved, should be cleared.
15.4.3 Memory Status Register (MSTAT)
The memory status register (MSTAT) reports write-protect errors encountered during an external bus
access initiated by the memory controller. Writing ones to specific bits clears them; writing zeros has no
effect.
0 1
Field
Reset
R/W
Addr
This register is affected by HRESET but is not affected by SRESET.
Bits Name
0–7 — Reserved, should be cleared
8 WPER Write-protection error. Set when a write-protect error occurs on a write cycle to a write-protected
bank defined by BR x [WP].
9–15 — Reserved, should be cleared.
Freescale Semiconductor
Table 15-4. OR x Field Descriptions (continued)
Table 15-11. TRLX also doubles the wait-states programmed in SCY.
2 3 4 5
—
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x178
Figure 15-9. Memory Status Register (MSTAT)
Table 15-5. MSTAT Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
6 7 8 9
WPER
R/W
Table 15-5
Description
Memory Controller
15
—
describes MSTAT fields.
15-13