Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 614

Powerquicc family

Table of Contents

Serial Interface

Enabling Connections to the TSA

Each SCC and SMC can be independently enabled to connect to the TSA. The SCCs are connected to the

TSA by programming the SI clock route register SICR[SCx]; see

The SMCs are connected to the TSA by setting the mode register SIMODE[SMCx]; see

Section 20.2.4.2, "SI Mode Register (SIMODE)."

set to enable the individual TDM channels; see

Once the connections are made, the exact routing is determined in the SI RAM. See

The 512-byte SI RAM contains the SCC and SMC routing information for the TDM channels. The SI

RAM totals 128 32-bit entries—64 entries each for receive and transmit routing. Representing one time

slot, an entry controls from 1 to 16 bits/bytes and up to four strobe pins (all active high).

The TDM channel options with their corresponding SI RAM partitioning follow:

A single TDM channel with static routing—SI RAM is divided into Rx and Tx parts.

Two TDM channels with static routing—Rx and Tx RAMs are halved.

A single TDM channel with dynamic routing—Rx and Tx RAMs are halved.

• Two TDM channels with dynamic routing—Rx and Tx RAMs are quartered.

Section 20.2.4.1, "SI Global Mode Register (SIGMR)."

Control Logic

SIMODE[SMC1]=1

SIMODE[SMC1]=0

SIMODE[SMC2]=1

SIMODE[SMC2]=0

Figure 20-4. Enabling Connections through the SI

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Section 20.2.4.3, "SI Clock Route

The general mode register SIGMR[ENx] must also be

SIGMR[ENa]=1 to enable TDMa

SIGMR[ENb]=1 to enable TDMb

Non-Multiplexed Interface

(clocking paths not shown)

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