Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 32

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Number
33.3.2.1 Control Character Table, RCCM, and RCCR........................................................ 33-6
33.4 The PIP Registers........................................................................................................... 33-8
33.4.1 PIP Configuration Register (PIPC)............................................................................ 33-8
33.4.2 PIP Event Register (PIPE) ......................................................................................... 33-9
33.4.3 PIP Mask Register ................................................................................................... 33-10
33.4.4 PIP Timing Parameters Register (PTPR) ................................................................. 33-10
33.4.5 The Port B Registers ................................................................................................ 33-11
33.5 PIP Buffer Descriptors ................................................................................................. 33-12
33.5.1 The PIP Tx Buffer Descriptor (TxBD) .................................................................... 33-12
33.5.2 The PIP Rx Buffer Descriptor (RxBD).................................................................... 33-13
33.6 PIP CP Commands....................................................................................................... 33-14
33.7 Handshaking I/O Modes .............................................................................................. 33-15
33.7.1 Interlocked Handshake Mode .................................................................................. 33-15
33.7.2 Pulsed Handshake Mode.......................................................................................... 33-16
33.7.2.1 The BUSY Signal ................................................................................................ 33-17
33.7.2.2 Pulsed Handshake Timing ................................................................................... 33-17
33.8 Transparent Transfers................................................................................................... 33-19
33.9 Implementing Centronics............................................................................................. 33-19
33.9.1 PIP as a Centronics Transmitter............................................................................... 33-20
33.9.1.1 Centronics Tx Errors and the PIPE...................................................................... 33-21
33.9.2 PIP as a Centronics Receiver ................................................................................... 33-21
33.9.2.1 Centronics Rx Errors and the PIPE ..................................................................... 33-22
34.1 Features .......................................................................................................................... 34-2
34.2 Port A............................................................................................................................. 34-2
34.2.1 Port A Registers ......................................................................................................... 34-3
34.2.1.1 Port A Open-Drain Register (PAODR) ................................................................. 34-3
34.2.1.2 Port A Data Register (PADAT).............................................................................. 34-4
34.2.1.3 Port A Data Direction Register (PADIR) .............................................................. 34-4
34.2.1.4 Port A Pin Assignment Register (PAPAR) ............................................................ 34-5
34.2.2 Port A Configuration Examples................................................................................. 34-5
34.2.3 Port A Functional Block Diagrams............................................................................ 34-6
34.3 Port B ............................................................................................................................. 34-7
34.3.1 The Port B Registers .................................................................................................. 34-9
34.3.1.1 Port B Open-Drain Register (PBODR).................................................................. 34-9
34.3.1.2 Port B Data Register (PBDAT).............................................................................. 34-9
34.3.1.3 Port B Data Direction Register (PBDIR)............................................................. 34-10
34.3.1.4 Port B Pin Assignment Register (PBPAR) .......................................................... 34-11
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Contents
Title
Chapter 34
Parallel I/O Ports
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
Freescale Semiconductor