Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 291

Figure 10-1 is a block diagram of the system configuration and protection logic.
10.3 Multiplexing SIU Pins
Due to the limited number of pins available in the MPC885 package, some of the pins share functions.
Table 10-1 shows how functionality is controlled on each pin.
Name
TSIZ0/REG
BDIP/GPL_B5
RSV/IRQ2
KR/RETRY/IRQ4/SPKROUT
IRQ[3:6]
FRZ/IRQ6
CS6/CE1_B
CS7/CE2_B
WE0/BS_AB0/IORD
WE1/BS_AB1/IOWR
WE2/BS_AB2/PCOE
WE3/BS_AB3/PCWE
Freescale Semiconductor
Module
Configuration
Bus
Monitor
Periodic Interrupt
Timer
Software
Watchdog Timer
Clock
Decrementer
Timebase Counter
Figure 10-1. System Configuration and Protection Logic
Table 10-1. Multiplexing Control
Dynamically active if the transaction addresses a slave controlled by the
PCMCIA interface.
Programmed in SIUMCR.
Address matching and bank valid bits. When a transfer matches either memory
controller bank 6 or any PCMCIA bank mapped to slot B, CS6/CE1_B is
asserted. When a transfer matches either memory controller bank 7 or any
PCMCIA bank mapped to slot B, CS7/CE2_B is asserted.
Dynamically active depending on the machine (GPCM, UPMB, or PCMCIA
interface) assigned to control the required slave.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
TEA
Interrupt
Interrupt or
System Reset
Interrupt
Interrupt
Pin Configuration Control
System Interface Unit
10-3