Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 756

SCC BISYNC Mode
23. Write 0x2000_0000 to the CPM interrupt mask register (CIMR) to allow SCC2 to generate a
system interrupt. The CICR should also be initialized.
24. Write 0x00000020 to GSMR_H2 to configure a small receive FIFO width.
25. Write 0x00000008 to GSMR_L2 to configure CTS and CD to automatically control transmission
and reception (DIAG bits) and the BISYNC mode. Notice that the transmitter (ENT) and receiver
(ENR) are not yet enabled.
26. Set PSMR2 to 0x0600 to configure CRC16, CRC checking on receive, and normal operation (not
transparent).
27. Write 0x00000038 to GSMR_L2 to enable the transmitter and receiver. This additional write
ensures that ENT and ENR are enabled last.
Note that after 5 bytes are sent, the TxBD is closed. The buffer is closed after 16 bytes are received. Any
received data beyond 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared.
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MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor