Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 145

Powerquicc family

Table of Contents

The following is a list of the MPC8xx core main features:

32-bit implementation of PowerPC architecture features

— User-level instruction set (not including floating-point instructions)

— Thirty-two, 32-bit general-purpose registers (GPRs)

— Registers required to support PowerPC user-level instruction set (except floating-point

instructions). These include the integer exception register (XER), condition register (CR), link

— Time base upper and time base lower registers (TBU and TBL)

— A subset of the supervisor-level registers for compliance with the following PowerPC models:

– Configuration—Machine state register (MSR)

– Exception model—Save/restore registers 0 and 1 (SRR0 and SRR1), DSI status register

(DSISR), data address register (DAR)

— Core-specific registers compliant with PowerPC architecture

— Static branch prediction

— Precise exception model that includes the subset of the PowerPC exceptions which supports the

instruction set and memory management. The MPC885 implements all PowerPC asynchronous

exceptions (interrupts)—system reset, machine check, decrementer, and external interrupts.

MPC885-specific exceptions are PowerPC-compliant.

— Separate 32-entry instruction and data translation lookaside buffers (TLBs)

Core-specific features

— Fully static design

— Additional registers that support the MPC885-specific features

— The ability to optimally issue and retire one instruction per clock cycle

— Out-of-order execution and in-order completion

— Extensive debug/testing support

Basic Structure of the Core

The MPC885 core consists of the following subunits:

Instruction unit (sequencer)—Consists of the branch processing unit (BPU), the instruction queue,

and the exception handling mechanism.

Execution units—These consist of the following:

— Integer unit—Implements all integer arithmetic and logical instructions defined by the

PowerPC architecture:

— Load/store unit (LSU)—Implements all load and store instructions except floating-point

load/store instructions. Note that because the MPC885 does not implement floating-point load

and store instructions, this document refers to integer load/store instructions simply as

load/store instructions.

Freescale Semiconductor

MPC885 PowerQUICC Family Reference Manual, Rev. 2

The MPC8xx Core