Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 514

Powerquicc family

Table of Contents

Memory Controller

Page Mode Extended Data-Out Interface Example

Figure 15-63

shows the configuration for a 1-Mbyte, 32-bit wide memory system using two 256K x 16-bit

page mode EDO DRAMs. Also shown is the physical connection between UPMB and the EDO DRAMs.

The CS2 signal controlled by BRx is connected to both RAS signals. The BS_B[0:1] signals map to

D[0:15] and BS_B[2:3] map to D[16:31]. For this connection, GPL_B1 is connected to the memory device

OE pins. The refresh rate calculation is based on a 25-MHz baud rate generator clock and the DRAM that

requires a 512-cycle refresh every 8 ms.

This system has no external masters, and thus the MPC885 is configured to perform address multiplexing

Follow these steps to configure a system for EDO DRAM:

1. Determine the system architecture, which includes the MPC885 and the memory system as shown

in the example in

2. Use the blank work sheet in

Figure 15-64

3. Translate the timing diagrams into RAM words for each memory access type. The bottom half of

the figures show the RAM array contents that handle each of the possible cycles; each column

represents a different word in the RAM array. A blank cell indicates a don't care bit (typically

programmed to logic 1 to conserve power).

4. Define the UPMB (or UPMA) parameters that control the memory system in the following

sequence. For additional details, see

— Program the RAM array using MCR and MDR. The RAM word must be written into the MDR

— Initialize ORx and BRx for the required DRAM device address mapping.

Figure 15-63. EDO DRAM Interface Connection

Figure 15-70

Figure 15-69

can be used as a reference.

command is issued to the MCR. Repeat this step for all RAM word entries.

MPC885 PowerQUICC Family Reference Manual, Rev. 2

for timing diagrams. The timing diagrams in

Freescale Semiconductor