Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 920

Parallel I/O Ports
34.1 Features
The following lists the main features of the parallel I/O ports:
• Port A is 16 bits.
• Port B is 18 bits. Port B is shared with the PIP, which is described in
Port (PIP)."
• Port C is 12 bits.
• Port D is 13 bits.
• Port E is 18 bits.
• All ports are bidirectional.
• At Power-ON Reset, CPM Port-B pins states are not predictable and are in an undefined state. CPM
Port-B pins require an output clock in order to be initialized, and therefore will be configured to
three-state mode after the DPLL is locked and output clock is present for two clock cycles. Ports
A, C, D and E are initialized asynchronously, and will therefore power-up in the three-state mode
immediately after power is applied and Power-ON Reset (POR) is asserted.
• All ports have alternate on-chip peripheral functions and all signal values can be read while the
signal is connected to an on-chip peripheral.
• Ports A, B, and E have open-drain capability.
• Port C has 12 interrupt input signals.
34.2 Port A
Port A signals are configured as follows in the port A pin assignment register (PAPAR):
• General-purpose I/O signal (the corresponding PAPAR[DDn] = 0)
• Dedicated on-chip peripheral signal (PAPAR[DDn] = 1)
PAPAR and the port A data direction register (PADIR) are cleared at reset, thus configuring all port A
signals as general-purpose input signals.
Signal
PAPAR[DD n ] = 0
(General I/O)
PA15 PORT A15
PA14 PORT A14
PA13 PORT A13
PA12 PORT A12
PA11 PORT A11
PA10 PORT A10
34-2
Table 34-1
Table 34-1. Port A Pin Assignment
PAPAR[DD n ] = 1
1
PADIR[DR n ] = 0
USBRXD
USBOE
RXD2
TXD2
RXD4
TIN4/CLK7
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Chapter 33, "Parallel Interface
shows defaults for port A signal options.
Pin Function
Input to On-Chip Peripherals
PADIR[DR n ] = 1
—
—
—
—
MII1-TXD0
RMII1-TXD0
MII1-TXER
(Default)
GND
—
GND
—
RXD4 = GND
TIN4/CLK7 = BRG04
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