Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 759

Powerquicc family

Table of Contents

Although the MPC885 contains DPLLs that allow Manchester encoding and decoding, these DPLLs were

not designed for ethernet rates. Therefore, the MPC885 ethernet controller bypasses the on-chip DPLLs

and uses the external system interface adaptor on the EEST instead. The on-chip DPLL cannot be used for

low-speed (1-Mbps) ethernet either because it cannot properly detect start-of-frame or end-of-frame.

Note that the CPM of the MPC885 requires a minimum system clock frequency of 24 MHz to support

The following list summarizes the main features of the SCC in ethernet mode:

Performs MAC layer functions of ethernet and IEEE 802.3

Performs framing functions

— Preamble generation and stripping

— Destination address checking

— CRC generation and checking

— Automatically pads short frames on transmit

— Framing error (dribbling bits) handling

Full collision support

— Enforces the collision (jamming)

— Truncated binary exponential backoff algorithm for random wait

— Two nonaggressive backoff modes

— Automatic frame retransmission (until the retry limit is reached)

— Automatic discard of incoming collided frames

— Delay transmission of new frames for specified interframe gap

Maximum 10 Mbps bit rate

Optional full-duplex support

Back-to-back frame reception

Detection of receive frames that are too long

Multibuffer data structure

Supports 48-bit addresses in three modes

— Physical–One 48-bit address recognized or 64-bin hash table for physical addresses

— Logical–64-bin group address hash table plus broadcast address checking

— Promiscuous–Receives all addresses, but discards frame if REJECT is asserted

Up to eight parallel I/O pins can be sampled and appended to any frame

Optional heartbeat indication

Transmitter network management and diagnostics

— Lost carrier sense

Freescale Semiconductor

MPC885 PowerQUICC Family Reference Manual, Rev. 2

SCC Ethernet Mode