Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 385

External Bus Interface
The timing chart in Figure 13-8 shows the basic timing of a single-beat write cycle with no wait states.
CLKOUT
BR
Receive BG and BB negated
BG
Assert BB, drive address and assert TS
BB
A[0:31]
R/W
TSIZ[0:1], AT[0:3]
BURST
TS
Data
TA
Data is sampled
Figure 13-8. Basic Timing: Single-Beat Write Cycle, Zero Wait States
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 13-11