Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 886

2
I C Controller
A master write performed by the MPC885 occurs as follows:
1. Set the master's I2COM[STR]. The transfer starts when the SDMA channel loads the transmit
FIFO with data and the I
2
2. The I C master generates a start condition—a high-to-low transition on SDA while SCL is
high—and the transfer clock SCL pulses for each bit shifted out on SDA. If the master transmitter
detects a multiple-master collision (by sensing a '0' on SDA while sending a '1'), transmission
stops and the channel reverts to slave mode. A maskable interrupt is sent to the master's core so
software can try to retransmit later.
3. The slave acknowledges each byte and writes to its current receive buffer until a new start or stop
condition is detected.
4. After sending each byte, the master monitors the acknowledge indication. If the slave receiver fails
to acknowledge a byte, transmission stops and the master generates a stop condition—a
low-to-high transition on SDA while SCL is high.
2
32.3.2 I C Loopback Testing
When in master mode, an I
2
I C controller simply issues a write request directed to its own address (programmed in I2ADD). The
master's receiver monitors the transmission and reads the transmitted data into its receive buffer. Loopback
operation requires no special register programming.
2
32.3.3 I C Master Read (Slave Write)
Before initiating a master read with the MPC885, prepare a transmit buffer of size n+1 bytes, where n is
the number of bytes to be read from the slave. The first transmit byte should be initialized to the slave
address with R/W = 1. The next n transmit bytes are used strictly for timing and can be left uninitialized.
Configure suitable receive buffers and BDs to receive the slave's transmission.
If the MPC885 is the slave target of the read, prepare the I
setting I2COM[STR]. Figure 32-5
SDA
Note: After the nth data byte, the master does not acknowledge the slave.
A master read performed by the MPC885 occurs as follows:
1. Set the master's I2COM[STR] to initiate the read. The transfer starts when the SDMA channel
loads the transmit FIFO with data and the I
2. The slave detects a start condition on SDA and SCL.
32-4
2
C bus is not busy.
2
C controller supports loopback operation for master write requests. The master
shows the timing for a master read.
S
T
A
R
T
Device Address
2
Figure 32-5. I C Master Read Timing
MPC885 PowerQUICC Family Reference Manual, Rev. 2
2
C transmit buffers and BDs and activate it by
A
C
K
R
Data Byte
2
C bus is not busy.
N
O
S
A
T
C
O
K
P
Freescale Semiconductor