Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 930

Powerquicc family

Table of Contents

Parallel I/O Ports

PCPAR[DD n ] = 0

PCDIR[DR n ] = 1

or PCSO[ n ] = 0

PDPAR[UT] = 1 and UTMODE[RSL] = 0, see

PDPAR[UT] = 1 and UTMODE[RSL,SPLIT] = 0b11, see

PCDIR and PCPAR bits are cleared at system reset, making all port signals general-purpose inputs. The

CPM interrupt mask register (CIMR) (see

so port C I/O signals left floating do not cause false interrupts.

General-purpose port C I/O signals can be accessed through PCDAT where written data is stored in an

output latch. If a port C signal is configured as an output, output latch data is gated onto the port signal.

Reading PCDAT reads the value of the port signal itself. For port C input signals, data written to PCDAT

is stored in the output latch but cannot reach the port signal. In this case, when the PCDAT register is read,

the state of the port signal is read.

The following steps configure port C signals as general-purpose outputs. When the signal is configured as

an output, port C interrupts are not generated.

1. Write the corresponding PCPAR bit with a 0.

2. Write the corresponding PCDIR bit with a 1.

3. Write the corresponding PCSO bit with a zero (for clarity).

4. The corresponding PCINT bit is a 'don't care.'

Table 34-11. Port C Pin Assignment

PCDIR[DR n ] = 0

PCDIR[DR n ] = 0 PCDIR[DR n ] = 1

and PCSO[ n ] = 1

Section 42.2.3, "Port C—MasterRxClav/Slave TxClav Signal."

Section 35.5.3, "CPM Interrupt Mask

MPC885 PowerQUICC Family Reference Manual, Rev. 2

PCPAR[DD n ] = 1

Section 42.2.3, "Port C—MasterRxClav/Slave TxClav

Input to On-Chip

L1TSYNCB = PD13

L1RSYNCB = PD12

L1TSYNCA = PD15

L1RSYNCA = PD14

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