Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 938

Parallel I/O Ports
34.5.1.3 Port D Pin Assignment Register (PDPAR)
The ATM and UT bits are included in the PDPAR register, shown in
cleared at system reset.
0 1
Field ATM UT
Reset 0 0
Oper
Addr
The fields in the PDPAR register are described in
Bits Name
0 ATM ATM global enable
0 =Disable ATM SAR functionality
1 =Enable ATM SAR functionality
1 UT UTOPIA enable. Determines whether the parameter RAM's page 4 (SCC4) operates in serial or
UTOPIA mode.
0 =Serial mode using SCC4
1 = UTOPIA mode
2 — Reserved
3–15 DD n Signal assignment. Determines whether the signal is a general-purpose I/O signal or performs a
dedicated function.
0 =General-purpose I/O. The peripheral functions of the signal are not used.
1 =Dedicated peripheral function. The signal performs the function assigned by the internal
module.
34.6 Port E
All port E signals can be open-drain. They are configured independently as general-purpose I/O signals if
the corresponding bit in the PEPAR is cleared, and they are configured as dedicated on-chip peripheral
signals if the corresponding PEPAR bit is set. When configured as a general-purpose I/O signal, the
direction of that pin is determined by the corresponding control bit in the PEDIR. The port I/O signal is
configured as an input if the corresponding PEDIR bit is cleared, and it is configured as an output if the
corresponding PEDIR bit is set. All PEPAR bits and PEDIR bits are cleared by hardware reset, thus
configuring all port E signals as general-purpose inputs.
If a port E signal is selected as a general-purpose I/O signal, it can be accessed through the PEDAT where
data is stored in an output latch. If a port E signal is configured as an output, the output latch data is gated
onto the port signal. When PEDAT is read, the port signal itself is read.
34-20
2 3 4 5 6
— DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
0 0 0 0
OFFSET TO IMMR: 0X972 (PDPAR)
Figure 34-18. Port D Pin Assignment Register (PDPAR)
Table 34-21. PDPAR Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Figure
7 8 9 10
0 0 0 0
R/W
Table 34-21.
Description
Table 34-22 describes port E signal options.
34-18. The PDPAR register is
11 12 13 14 15
0 0 0 0 0
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