Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 236

Instruction and Data Caches
used block is selected for replacement. If the replacement block is marked modified-valid, it is temporarily
stored in a copyback buffer to be written to memory later. Locked cache blocks are never replaced.
After a cache block has been selected, the word-aligned physical address of the requested data is sent to
the SIU with a 4-word burst transfer read request. The SIU arbitrates for the bus and initiates the burst read.
The transfer begins with the aligned word containing the requested data (critical word first), followed by
the remaining words of the cache block (if any), then by any remaining words at the beginning of the block
(wrap-around).
The critical word is simultaneously written to the burst buffer and forwarded to the load/store unit, thus
minimizing stalls due to cache fill latency. The data cache is not blocked to internal accesses while the load
(caused by a cache miss) completes. This functionality is sometimes called 'hits under misses,' because
the cache can service a hit while a cache miss fill is waiting to complete. If no bus errors are encountered
during the 4-word cache block load, the burst buffer is written to the cache array (provided the cache array
is not busy servicing a hit) and the cache block is marked unmodified-valid.
If a bus error is encountered while loading the requested data (the critical word), a machine check
exception is generated. If a bus error occurs while loading subsequent words in the cache block, the cache
block is marked invalid.
After the cache block with the requested data has been loaded from memory, the modified-valid cache
block in the copyback buffer is sent to the SIU to be written to memory. If a bus error is encountered during
the copyback, a machine check exception is generated (the copyback error is an imprecise exception). The
address and data in the copyback buffer can be read as specified in
Tags and Copyback Buffer."
7.6.3 Write-Through Mode
In write-through mode, store operations always update memory. The write-through mode is used when
external memory and internal cache images must always agree. Write-through mode provides a lower
worst case exception latency at the expense of average performance (for example, if it does not have to
perform flush accesses).
7.6.3.1 Data Cache Store Hit in Write-Through Mode
In the case of a data cache store hit in write-through mode, the data is written into both the cache block
and to memory. The LRU state of the set is updated, but the state bits remain unchanged. If a bus error is
encountered during the write operation to memory, the cache block is still updated, but a machine check
exception is generated.
7.6.3.2 Data Cache Store Miss in Write-Through Mode
In the case of a store miss in write-through mode, the data is only written to memory, not to the data cache.
This is sometimes called a no-allocate store miss because the data cache does not allocate a cache block
in the cache array for the missed store operation. The state and LRU bits remain unchanged. If a bus error
is encountered during the write operation to memory, a machine check exception is generated.
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MPC885 PowerQUICC Family Reference Manual, Rev. 2
Section 7.3.2.1, "Reading Data Cache
Freescale Semiconductor