Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 638

Powerquicc family

Table of Contents

Serial Interface

In addition to the 144-Kbps ISDN 2B+D channels, the GCI provides two channels for maintenance and

B1 is a 64-Kbps bearer channel

B2 is a 64-Kbps bearer channel

M is a 64-Kbps monitor channel

D is a 16-Kbps signaling channel

C/I is a 48-Kbps command/indication channel (includes A and E bits)

The M channel is used to transfer data between layer-1 devices and the control unit (the core) and the C/I

channel is used to control activation/deactivation procedures or to switch test loops by the control unit. The

M and C/I channels of the GCI bus should be routed to SMC1 or SMC2, which have modes to support the

channel protocols. The MPC885 can support any channel of the GCI bus in the primary rate by modifying

the SI RAM programming.

The GCI supports the CCITT I.460 recommendation as a method for data rate adaptation since it can

access each bit of the GCI separately. The current-route RAM specifies which bits are supported by the

interface and serial controller. The receiver accepts only the bits that are enabled by the SI RAM. The

transmitter sends only the bits that are enabled by the SI RAM and does not drive L1TXDx otherwise.

L1TXDx is an open-drain output and should be pulled high externally.

The MPC885 supports contention detection on the D channel of the SCIT bus. When the MPC885 has data

to send on the D channel, it checks an SCIT bus bit that is marked with a special route code (usually, bit 4

of C/I channel 2). The physical layer device monitors the physical layer bus for activity on the D channel

and indicates on this bit that the channel is free. If a collision is detected on the D channel, the physical

layer device drives bit 4 of C/I channel 2 to logic high. The MPC885 then aborts its transmission and

resends the frame when this bit is driven to logic low again. This procedure is automatically handled for

the first two buffers of a frame.

GCI Activation/Deactivation

In the deactivated state, the clock pulse is disabled and the data line is at a logic one. The layer-1 device

activates the MPC885 by enabling the clock pulses and sending an indication on the C/I channel 0. To

report the arrival of a valid indication in the SMC's RxBD, the CPM sends a maskable interrupt to the core.

When the core activates the line, the data output of L1TXDx should be programmed to zero by setting

SIMODE[STZx]. Code 0 (command timing TIM) is sent on C/I channel 0 to the layer-1 device until STZx

is cleared. The physical layer device resumes the clock pulses and gives an indication on C/I channel 0.

The core should then clear STZx to enable data output.

Programming the GCI Interface

The two GCI interface modes, normal and SCIT, are described in the following sections.

For normal mode operation, first program the channels' SIMODE[DSCx, FEx, CEx, RFSDx] for

GCI/SCIT mode, defining the sync pulse to GCI sync for framing and the data clock as one-half the input

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Freescale Semiconductor