Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 297

0
Field
Reset
R/W
SPR
16 17 18
Field — IEXT ITMT
Reset
R/W
SPR
Table 10-5 describes the TESR fields.
Bits Name
0–17 — Reserved, should be cleared.
18 IEXT Instruction external transfer error acknowledge. Set if the cycle is terminated by an externally
generated TEA when an instruction fetch is initiated.
19 ITMT Instruction transfer monitor timeout. Set if the cycle is terminated by a bus monitor timeout when
an instruction fetch is initiated.
20–25 — Reserved, should be cleared.
26 DEXT Data external transfer error acknowledge. Set if the cycle is terminated by an externally
generated TEA signal when a data load or store is requested by an internal master.
27 DTMT Data transfer monitor timeout. Set if the cycle is terminated by a bus monitor timeout when a data
load or store is requested by an internal master.
28–31 — Reserved
10.4.5 Register Lock Mechanism
To provide protection of the SIU registers against uncontrolled shutdown, a register locking mechanism is
included. These registers can be write-protected in a set of associated key registers. The MPC885 key
registers are shown in Table
Offset
0x300 TBSCRK—Timebase status and control register key
0x304 TBREFAK—Timebase reference register A key
Freescale Semiconductor
xxxx_xxxx_xxxx_xxxx
(IMMR & 0xFFFF0000) + 0x020
19 20 21 22 23
—
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x022
Figure 10-5. Transfer Error Status Register (TESR)
Table 10-5. TESR Field Descriptions
10-6.
Table 10-6. Key Registers
Name
System Integration Timers Keys
MPC885 PowerQUICC Family Reference Manual, Rev. 2
—
R/W
24 25 26 27
DEXT DTMT
R/W
Description
System Interface Unit
15
28 29 30 31
—
Size
32 bits
32 bits
10-9