Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 942

Parallel I/O Ports
This register is affected by HRESET but is not affected by SRESET.
Bits Name
0–13 — Reserved
14 –31 DR n Port E data direction. Configures port E signals as inputs or outputs when functioning as
general-purpose I/O; otherwise, used to select the peripheral function.
0 Select the signal for general-purpose input, or select peripheral function 0.
1 Select the signal for general-purpose output, or select peripheral function 1.
34.6.1.4 Port E Pin Assignment Register (PEPAR)
The port E pin assignment register (PEPAR) configures signals as general-purpose I/O or dedicated for use
with a peripheral. The MII/RMII configuration bits of both Fast Ethernet Controllers are included in the
PEPAR register, shown in
0 1 2
Field
Reset — — —
R/W
Addr
16 17 18
Field DD16 DD17 DD18 DD19 DD20 DD21 DD22 DD23 DD24 DD25 DD26 DD27 DD28 DD29 DD30 DD31
Reset 0 0 0
R/W R/W R/W R/W
Addr
This register is affected by HRESET but is not affected by SRESET.
Bits Name
0–13 — Reserved
DD n
14 –31 Port E pin assignment. Determines whether a signal is configured for general-purpose I/O or
dedicated peripheral function.
0 General-purpose I/O. The peripheral functions of the signal are not used.
1 Dedicated peripheral function. The signal is used by the internal module. The on-chip
34-24
Table 34-25. PEDIR Bit Descriptions
Figure 34-22. The PEPAR register is cleared at system reset.
3 4 5 6
— — — —
19 20 21 22
0 0 0 0
R/W R/W R/W R/W
Figure 34-22. Port E Pin Assignment Register (PEPAR)
Table 34-26. PEPAR Bit Descriptions
peripheral function to which it is dedicated can be determined by other bits such as those in
the PEDIR and PESO.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Table 34-25
Description
7 8 9 10
—
— — — —
—
0xACC
23 24 25 26
0 0 0 0
R/W R/W R/W R/W
0xACE
Table 34-26
Description
describes PEDIR bits.
11 12 13 14 15
DD14 DD15
— — — 0
R/W R/W
27 28 29 30 31
0 0 0 0
R/W R/W R/W R/W R/W
describes PEPAR bits.
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