Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 312

System Interface Unit
Figure 10-20 shows TBL.
0
Field
Reset
R/W
SPR
Table 10-17 describes TBL fields.
Bits Name
0–31 TBL Timebase lower. The value in this field is used as the lower part of the timebase register.
10.9.2 Timebase Reference Registers (TBREFA and TBREFB)
TBREFA and TBREFB are associated with TBL. When the contents of TBL matches a reference register,
a reference event is signaled in TBSCR[REFA] or TBSCR[REFB]. These events can generate interrupts,
if enabled. Note that TBREFA and TBREFB are keyed registers. They must be unlocked in TBREFAK
and TBREFBK before they can be written.
0
Field
Reset
R/W
Addr TBREFA (IMMR & 0xFFFF0000) + 0x204/TBREFB (IMMR & 0xFFFF0000) + 0x208
16
Field
Reset
R/W
Addr TBREFA (IMMR & 0xFFFF0000) + 0x206/TBREFB (IMMR & 0xFFFF0000) + 0x20A
Figure 10-21. Timebase Reference Registers (TBREFA and TBREFB)
These registers are affected by HRESET but are not affected by SRESET.
TBREFA/TBREFB fields.
Bits Name
0–31 TBREFA Timebase reference A. Represents the 32-bit reference value for TBL.
0–31 TBREFB Timebase reference B. Represents the 32-bit reference value for TBL
10-24
268 (Read)/284 (Write)
Figure 10-20. Timebase Lower Register (TBL)
Table 10-17. TBL Field Descriptions
TBREFA/TBREFB
TBREFA/TBREFB
Table 10-18. TBREFA/TBREFB Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
TBL
—
R/W
Description
—
R/W
—
R/W
Table 10-18
Description
31
15
31
describes
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