Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 247

Data/Instruction Fetch
Compare address
TLB reload (read page
description from external
memory to TLB)
8.3.3 TLB Operation
Each TLB contains pointers to pages in physical memory where data is indexed by the EPN. TLBs entries
can have different page sizes. The entry page size determines which EA bits are compared and how many
of its lsbs pass untranslated as physical address bits.
For a 4-Kbyte page, four subpage validity flags are supported, allowing any combination of 1-Kbyte
subpages to be mapped. For any other page size, all of these flags should have the same value.
Programming non-4-Kbyte pages with different valid bits is a programming error. Subpage validity flags
can be manipulated to implement 1–4-Kbyte pages or any other combination of 1-Kbyte subpages.
However, all subpages of an effective page frame must map to the same physical page. During translation,
the EA, the privilege level (MSR[PR]), and CASID are provided to the TLB, as shown in
the TLB, the EA and CASID are compared with each entry's EPN and ASID. The CASID is compared
only when the matching entry is programmed as unshared. See
Freescale Semiconductor
32-bit EA is generated
with TLB
(0 clock penalty)
entries
TLB
Yes
Hit
?
No
(20–23 clock penalty
@ one wait-state
external memory)
Use page description from TLB
Figure 8-2. Flow of Load/Store Access
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Is page
No
valid
?
Yes
Access permitted
No
by page protection
?
Yes
Table 8-12
Memory Management Unit
TLB Error Exception
Figure 8-3. In
and Table 8-13.
8-5