Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 179

Name
Compare Immediate
Compare
Compare Logical Immediate
Compare Logical
1
Implementation Note: In these instructions, the L bit is applicable for 64-bit implementations. For the MPC885, if
L = 1 the instruction form is invalid. The core ignores this bit and, therefore, the behavior when L = 1 is identical to the
valid form instruction with L = 0.
The crfD operand can be omitted if the result of the comparison is to be placed in CR0. Otherwise the
target CR field must be specified in the instruction crfD field.
For more information refer to Appendix F, "Simplified Mnemonics," in the Programming Environments
Manual.
5.2.4.1.3 Integer Logical Instructions
The logical instructions shown in
CR update enabled and instructions andi. and andis. set CR field CR0 to characterize the result of the
logical operation. These fields are set as if the sign-extended low-order 32 bits of the result were
algebraically compared to zero. Logical instructions without CR update and the remaining logical
instructions do not modify the CR. Logical instructions do not affect the XER[SO], XER[OV], and
XER[CA] bits.
For simplified mnemonics examples for the integer logical operations see Appendix F, "Simplified
Mnemonics," in the Programming Environments Manual.
Name
AND Immediate
AND Immediate Shifted
OR Immediate
OR Immediate Shifted
XOR Immediate
XOR Immediate Shifted
AND
OR
XOR
NAND
NOR
Freescale Semiconductor
Table 5-3. Integer Compare Instructions
cmpi
cmp
cmpli
cmpl
Table 5-4 perform bit-parallel operations. Logical instructions with the
Table 5-4. Integer Logical Instructions
andi.
andis.
ori
oris
xori
xoris
and (and.)
or (or.)
xor (xor.)
nand (nand.)
nor (nor.)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Mnemonic
crfD,L,rA,SIMM
crfD,L,rA,rB
crfD,L,rA,UIMM
crfD,L,rA,rB
Mnemonic
rA,rS,UIMM
rA,rS,UIMM
rA,rS,UIMM
rA,rS,UIMM
rA,rS,UIMM
rA,rS,UIMM
rA,rS,rB
rA,rS,rB
rA,rS,rB
rA,rS,rB
rA,rS,rB
MPC885 Instruction Set
1
Syntax
Syntax
5-9