Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 594

SDMA Channels and IDMA Emulation
19.3.3.1 DMA Channel Mode Registers (DCMR)
Located in each IDMA's parameter RAM, the DMA channel mode registers (DCMR) configure the
peripheral port size, the source and destination type of the transfer, and the address mode (cycle mode) of
the IDMA channels. Figure 19-5
0
Field
Reset
R/W
Addr
Table 19-5 describes DCMR fields.
Bits Name
0–10 — Reserved, should be cleared.
11–12 SIZE Peripheral port size. Determines the operand transfer size per DREQ x assertion for
peripheral/memory transfers, but not for memory/memory transfers. (For memory/memory transfers
the size is determined only by address alignment and the amount of data remaining to be
transferred.)
00 Word length
01 Half-word length
10 Byte length
11 Reserved
Note that the memory port size is transparent to the IDMA. The SIU emulates a 32-bit port size
regardless of the actual memory port size.
13–14 S/D Source/destination. Defines the source and destination—memory or peripheral.
00 Read from memory; write to memory
01 Read from peripheral; write to memory
10 Read from memory; write to peripheral
11 Reserved
Note that for memory/memory accesses, the CP automatically increments the address and does not
use SDACK n .
15 SC Single-cycle. Selects single- or dual-cycle mode
0 Dual-cycle (dual-address) mode
1 Single-cycle (single-address) mode
19-8
shows the register format.
—
0
R
IDMA x Base + 0x02
Figure 19-5. DMA Channel Mode Register (DCMR)
Table 19-5. DCMR Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
10 11
SIZE
0
R/W
Description
12 13 14 15
S/D SC
0 0
R/W R/W
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