Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 582

Communications Processor
The RISC timer table parameter RAM holds the general timer parameters.
map.
Table 18-12. RISC Timer Table Parameter RAM Memory Map
1
Offset Name Width
0x00 TM_BASE Hword RISC timer table base address. The actual timers are a small block of memory in the
0x02 TM_PTR Hword RISC timer table pointer. Only the CP uses this register to point to the next timer
0x04 R_TMR Hword RISC timer mode register. Only the CP uses this register to store the mode of the timer,
0x06 R_TMV Hword RISC timer valid register. Only the CP uses this register to determine whether a timer
0x08 TM_CMD Word RISC timer command register. Used as a parameter location when
0x0C TM_CNT Word RISC timer internal count. Tick counter that the CP updates after each tick or after the
1
From timer base address (IMMR + 3DB0)
18.8.3.1 RISC Timer Command Register (TM_CMD)
Figure 18-9 shows the TM_CMD register.
0 1
Field V R PWM
16
Field
Table 18-13 describes TM_CMD fields.
Bits Name
0 V
1 R
18-16
dual-port RAM. TM_BASE is the offset from the beginning of the dual-port RAM where
that block of memory resides. Four bytes must be reserved at the TM_BASE for each
timer used, (64 bytes if all 16 timers are used). If fewer than 16 timers are used, timers
should be allocated in ascending order to save space. For example, only 8 bytes are
required if two timers are needed and RISC timers 0 and 1 are enabled.
TM_BASE should be word-aligned.
accessed in the timer table. Do not modify this register.
one-shot (0) or restart (1). Do not modify this register directly; it is modified indirectly
via TM_CMD and the
SET TIMER
is currently enabled. If the corresponding timer is enabled, a bit is 1. Do not modify this
register directly; it is modified indirectly via TM_CMD and the
Write this location before issuing
Section 18.8.3.1, "RISC Timer Command Register (TM_CMD)."
timer table is scanned. It is updated if the CP's internal timer is enabled, regardless of
whether any of the 16 timers are enabled, and it can be used to track the number of
ticks the CP receives and responds to.
2 3
Figure 18-9. RISC Timer Command Register (TM_CMD)
Table 18-13. TM_CMD Field Descriptions
Valid. When set, this bit enables the timer. It should be cleared to disable the timer.
Restart. Should be set for an automatic restart or cleared for a one-shot timer operation.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Table 18-12
Description
command.
. The bits of this register are defined in
SET TIMER
—
Timer Period
Description
shows its memory
command.
SET TIMER
is issued.
SET TIMER
11 12 15
Timer Number
31
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