SDMA Channels and IDMA Emulation
19.3.4.1
Function Code Registers—SFCR and DFCR
The user programs an IDMA channel's source and destination function code registers (SFCR and DFCR)
with separate 3-bit function codes to tag the channel's source and destination accesses. The function code
registers also determine the byte-ordering convention.
0
Field
Addr
Table 19-8
describes the function code register bit settings.
Bits
Name
0–2
—
Reserved. Should be cleared.
3–4
BO
Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-fly,
it takes effect at the beginning of the next frame (Ethernet, HDLC, and transparent) or at the beginning
of the next BD. See
00 Reserved
01 Modified little-endian
1x Big-endian or true little-endian
5–7
AT[1–3] Address type 1–3. Holds the function code for an IDMA channel memory access. Note AT[0] is driven
high to identify the access as a DMA type. Note that for the last IDMA cycle, the terminal count code
AT[0–3] = 0xF replaces the user-defined function code signaling the end of transfer to the peripheral.
19.3.4.2
Auto-Buffering and Buffer-Chaining
Buffer-chaining is designed to move large amounts of noncontiguous blocks of data. Even though each
block needs a separate BD, the BDs can be chained together and serviced as a group. Auto-buffering is
used to repeatedly service a BD chain. Note that a chain can range from one BD to the whole BD table in
length.
Setting the CM bit (continuous mode) in a BD's status-and-control field enables auto-buffering; clearing
the CM bit enables buffer-chaining (normal mode). The CM bit must be explicitly programmed for each
BD.
When auto-buffering, the descriptor's V bit will not be cleared after CPM processing—the BD remains
valid for immediate transfer as the current BD pointer cycles through the table. When buffer-chaining, the
CPM invalidates the current BD after processing to allow the user (the core) to safely manipulate the
contents of the buffer and modify its BD. Note that the V bit behavior is the only difference between
auto-buffering and buffer-chaining—auto-buffering can be thought of as continuous buffer-chaining. One
use of auto-buffering is for continuous monitoring of an external instrument, such as an A/D converter.
Set the L bit (last) in the status-and-control field to mark the last BD of a chain. When the CPM completes
a chain, it flags IDSR[DONE], triggering a maskable interrupt to the core. The I bit (individual BD
19-12
2
—
DFCR is at offset 0x02. SFCR is at offset 0x03.
Figure 19-9. Function Code Registers—SFCR and DFCR
Table 19-8. SFCR and DFCR Field Descriptions
Appendix A, "Byte
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Figure 19-9
shows the register format.
3
4
5
BO
Description
Ordering."
7
AT[1–3]
Freescale Semiconductor