Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 379

Signal Pins I/O
D[0:31] 32
Data Bus
TA 1
Transfer
Acknowledge
TEA 1
Transfer Error
Acknowledge
BI 1
Burst Inhibit
BR 1
Bus Request
BG 1
Bus Grant
Freescale Semiconductor
Table 13-1. MPC885 Signal Overview (continued)
1
Data
The data bus has the following byte lane assignments:
Data Byte Byte Lane
D[0:7] 0
D[8:15] 1
D[16:23] 2
D[24:31] 3
O Driven by the MPC885 when it is external bus master and it initiated a write transaction
to a slave device. For single-beat transactions, the byte lanes not selected for the transfer
by the A[30:31] and TSIZ[0:1] will not supply valid data.
I Driven by the slave in a read transaction. For single-beat transactions, the byte lanes not
selected for the transfer by the A[30:31] and TSIZ[0:1] will not be sampled by the
MPC885
Transfer Cycle Termination
I Driven by the slave device to which the current transaction is addressed. Indicates that
the slave received the data on the write cycle or returned data on the read cycle. If the
transaction is a burst, TA should be asserted for each beat.
O Driven by the MPC885 when the slave device is controlled by the on-chip memory
controller or PCMCIA interface.
I Driven by the slave device to which the current transaction is addressed. Indicates that
an error condition occurred during the bus cycle.
O Driven by the MPC885 when the internal bus monitor detects a bus error.
I Driven by the slave device to which the current transaction was addressed. Indicates that
the current slave does not support burst mode.
O Driven by the MPC885 when the on-chip memory controller controls the slave.
Arbitration
I Asserting BR when the internal arbiter is enabled indicates an external master is
requesting the bus.
O The MPC885 drives BR when the internal arbiter is disabled.
O When the internal arbiter is enabled, the MPC885 asserts BG to indicate that an external
master may assume bus mastership and begin a bus transaction. The device requesting
bus mastership should qualify BG to ensure it is the bus owner:
Qualified BG = BG & ~BB
I When the internal arbiter is disabled, BG is sampled and properly qualified by the
MPC885 when an external bus transaction is to be executed by the chip.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
External Bus Interface
13-5