Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 431

14.3.3 Time Base and Decrementer Clock (TMBCLK)
The time base and decrementer clock is generated either from the input frequency of the DPLL and
Interface (OSCLK) or the general system clock GCLK2. The SCCR[TBS] bit is used to select between
these two sources.
The MODCK[1:2] state at PORESET negation, the SCCR[TBS], and the DPLL multiplication factor
determine the input clock source and prescalar value for TMBCLK.
SCCR[TBS]
1
0
0
0
Note: TMBCLK prescalar is unpredictable (4 or 16) whenever MF lies between 2 to 2.33
14.4 Power Distribution
The various modules of the MPC885 are connected to four distinct power rails. These power rails have
different requirements, as explained in the following sections. The organization of the power rails is shown
in Figure 14-11.
Freescale Semiconductor
Table 14-6. TMBCLK Configuration
MODCK[1:2] at
PORESET
XX
0X
1X
1X
I/O Pad
Internal Logic
and
Clock Drivers
Analog
DPLL
V DDL V DDSYN
1.8 V
1.8 V
Figure 14-11. MPC885 Power Rails
MPC885 PowerQUICC Family Reference Manual, Rev. 2
MF Clock Source
X GCLK2
X OSCLK
1, 2 OSCLK
> 2 OSCLK
MPC885
OSCM, PIT,
TB,
DEC, SCCR,
PLPRCR,
and RSR
Clock Control
and Digital DPLL
Clocks and Power Control
TMBCLK Prescaler
16
4
16
4
TEXP
V DDH
3.3 V
14-15