Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 230

Instruction and Data Caches
7.4.2 Data Cache Block Touch (dcbt) and
Data Cache BlockTouch for Store (dcbtst)
The Data Cache Block Touch (dcbt) and Data Cache Block Touch for Store (dcbtst) instructions provide
potential system performance improvement through the use of software-initiated prefetch hints. The
MPC885 treats these instructions identically (that is, a dcbtst instruction behaves exactly the same as a
dcbt instruction on the MPC885).
The MPC885 loads the data into the cache when the effective address hits in the TLB, is permitted load
access from the addressed page, and is directed at a caching-allowed page. Otherwise, the MPC885 treats
these instructions as no-ops. The data brought into the cache as a result of this instruction is validated in
the same manner that a load instruction would be (that is, it is marked as unmodified-valid). Note that the
successful execution of the dcbt (or dcbtst) instruction affects the state of the TLB and cache LRU bits.
7.4.3 Data Cache Block Zero (dcbz)
The effective address is computed, translated, and checked for protection violations as defined in the
PowerPC architecture. The dcbz instruction is treated as a store to the addressed byte with respect to
address translation and protection.
If the block containing the byte addressed by the EA is in the data cache, all bytes are cleared, and the tag
is marked as modified-valid. If the block containing the byte addressed by the EA is not in the data cache
and the corresponding page is caching-allowed, the block is established in the data cache without fetching
the block from main memory, and all bytes of the block are cleared, and the tag is marked as
modified-valid.
The dcbz instruction executes regardless of whether the cache block is locked, but if the cache is disabled,
an alignment exception is generated. If the page containing the byte addressed by the EA is
caching-inhibited or write-through, the system alignment exception handler is invoked.
7.4.4 Data Cache Block Store (dcbst)
The effective address is computed, translated, and checked for protection violations as defined in the
PowerPC architecture. This instruction is treated as a load with respect to address translation and memory
protection.
If the address hits in the cache and the cache block is in the unmodified-valid state, no action is taken. If
the address hits in the cache and the cache block is in the modified-valid state, the modified block is written
back to memory and the cache block is placed in the unmodified-valid state.
If a bus error occurs while executing the dcbst instruction, DC_CST[CCER1] is set and a machine check
exception is generated. The data of the cache block flagged by the bus error is retrieved from the copyback
buffer, not from the data cache. See
more information.
The function of this instruction is independent of the memory/cache access attributes. The dcbst
instruction executes regardless of whether the cache is disabled or the cache block is locked.
7-18
Section 7.3.2.1, "Reading Data Cache Tags and Copyback Buffer,"
MPC885 PowerQUICC Family Reference Manual, Rev. 2
for
Freescale Semiconductor