Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 959

Table VI-1. Acronyms and Abbreviated Terms (continued)
Term
APC ATM pace control
ATM Asynchronous transfer mode
BD Buffer descriptor
BIP Bit interleaved parity
BIST Built-in self test
BRC Backward reporting cells
BT Burst tolerance
CBR Constant bit rate
CAM Content-addressable memory
CEPT Conférence Européene des Administrations des Postes et des Télécommunications (European
Conference of Postal and Telecommunications Administrations)
C/I Condition/indication channel used in the GCI protocol
CLP Cell loss priority
CP Communications processor
CP-CS Common part convergence sublayer
CPCS-PDU Common part convergence sublayer–protocol data unit
CPCS-UU Common part convergence sublayer–user to user information
CPI Common part indicators
CPM Communications processor module
CPS Cells per slot
CSMA Carrier sense multiple access
CSMA/CD Carrier sense multiple access with collision detection
DMA Direct memory access
DPLL Digital phase-locked loop
DPR Dual-port RAM
DRAM Dynamic random access memory
DSISR Register used for determining the source of a DSI exception
EA Effective address
EEST Enhanced Ethernet serial transceiver
EPROM Erasable programmable read-only memory
ESAR Enhanced segmentation and reassembly
FBP Free buffer pool
FIFO First-in-first-out (buffer)
Freescale Semiconductor
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Meaning
VI-3