Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 573

0
Field ERAM4K
Reset
R/W
Addr
Figure 18-4. RISC Microcode Development Support Control Register (RMDS)
RMDS fields are described in
Bits Name
0 ERAM4K Enable RAM microcode (at offset 4K)
0 Microcode may be executed only from the first 2 Kbytes of the dual-port RAM.
1 Microcode is also executed from the 2 Kbytes of the second half of the dual-port RAM with a
512-byte extension.
1–7 — Reserved, should be cleared.
18.6.3 CP Command Register (CPCR)
The MPC8xx core can issue commands to control communications via the CP command register (CPCR),
shown in Figure 18-5. The CP commands handle special cases, such as initializing or stopping a channel,
and are protocol-dependent.
When the core issues a command it sets CPCR[FLG]. When the command completes, the CP clears FLG
to signal the core for the next command. The core must wait for FLG to be cleared before issuing another
CP command. The core can, however, issue the CP reset command (CPCR = 0x8001) at any time,
regardless of FLG. Note that the CPCR has a different bit format for ATM operations; see
"Port-to-Port (PTP) Switching."
0 1
Field RST
Reset
R/W
Addr
Freescale Semiconductor
1
0000_0000_0000_0000
Table 18-5.
Table 18-5. RMDS Field Descriptions
3 4
— OPCODE
Figure 18-5. CP Command Register (CPCR)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
—
R/W
0x9C7
Description
7 8 11
CH_NUM
0
R/W
0x9C0
Communications Processor
7
Section 39.4,
12 14 15
— FLG
18-7