Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 369

Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Hard
Name
Reset
MII1_COL Hi-Z
Power supply
1
Pulled low if RSTCONF pulled down.
2
High until DPLL locked, then oscillates.
3
See Section 11.4, "TRST
12.3 Reset Behavior
The reset behavior of a subset of multiple-function pins depends on which signal function is active. The
SIU module configuration register (SIUMCR) programming determines which signal functions of this pin
subset are activated at reset; see
(but not all) of the SIUMCR default values are determined by the user-controlled hardware reset
configuration word; see
PORESET) is asserted, these pins immediately begin functioning as the signals selected in the SIUMCR.
The behavior of these signals is shown in
Freescale Semiconductor
Number Type
R10 Input
See Power
Figure 12-3
Considerations," and Section 54.6, "Recommended TAP Configuration."
Section 10.4.2, "SIU Module Configuration Register (SIUMCR)."
Section 11.3.1.1, "Hard Reset Configuration Word."
Table 12-3.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
MII1_COL —Media-independent interface 1, collision
VDDL—Power supply for the internal logic
VDDH—Power supply for the I/O buffers and certain parts of the
clock control
VDDSYN—Power supply of the PLL circuitry
GND—Ground for circuits, except for the PLL circuitry
VSSSYN, VSSSYN1—Ground for the PLL circuitry
External Signals
Some
When HRESET (or
12-39