Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 17

Paragraph
Number
14.1 Features .......................................................................................................................... 14-1
14.2 Clock Module ................................................................................................................ 14-3
14.2.1 External Reference Clocks......................................................................................... 14-3
14.2.2 Digital Phase Lock Loop and Interface ..................................................................... 14-4
14.2.3 DPLL Reset Configuration ........................................................................................ 14-6
14.2.4 Crystal Oscillator Support (EXTAL and XTAL)....................................................... 14-7
14.3 Clock Signals ................................................................................................................. 14-8
14.3.1 Clocks Derived from the DPLL Output..................................................................... 14-9
14.3.1.1 Internal General System Clocks (GCLK1C, GCLK2C, GCLK1, GCLK2)........ 14-10
14.3.1.2 Memory Controller and External Bus Clocks
(GCLK1_50, GCLK2_50, CLKOUT)............................................................. 14-11
14.3.1.3 CLKOUT Special Considerations: 1:2:1 Mode................................................... 14-13
14.3.1.4 Baud Rate Generator Clock (BRGCLK) ............................................................. 14-13
14.3.1.5 Synchronization Clock (SYNCCLK, SYNCCLKS) ........................................... 14-13
14.3.2 PIT Clock (PITCLK) ............................................................................................... 14-14
14.3.3 Time Base and Decrementer Clock (TMBCLK) ..................................................... 14-15
14.4 Power Distribution....................................................................................................... 14-15
14.4.1 I/O Buffer Power (VDDH) ...................................................................................... 14-16
14.4.2 Internal Logic Power (VDDL)................................................................................. 14-16
14.4.3 Clock Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1) ................................ 14-16
14.5 Power Control ............................................................................................................. 14-17
14.5.1 Normal High Mode.................................................................................................. 14-17
14.5.2 Normal Low Mode................................................................................................... 14-17
14.6 Clock and Power Control Registers............................................................................. 14-18
14.6.1 System Clock and Reset Control Register (SCCR) ................................................. 14-18
14.6.2 PLL and Reset Control Register (PLPRCR)............................................................ 14-21
15.1 Features .......................................................................................................................... 15-1
15.2 Basic Architecture.......................................................................................................... 15-4
15.3 Chip-Select Programming Common to the GPCM and UPM ....................................... 15-6
15.3.1 Address Space Programming..................................................................................... 15-7
15.3.2 Register Programming Order..................................................................................... 15-7
15.3.3 Memory Bank Write Protection................................................................................. 15-7
15.3.4 Address Type Protection............................................................................................ 15-7
15.3.5 8-, 16-, and 32-Bit Port Size Configuration............................................................... 15-7
Freescale Semiconductor
Contents
Title
Chapter 14
Clocks and Power Control
Chapter 15
Memory Controller
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
xvii