Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 773

Table 27-8 describes RxBD status and control fields.
Table 27-8. SCC Ethernet RxBD Status and Control Field Descriptions
Bits Name
0 E Empty
0 The buffer is full or stopped receiving data because an error occurred. The core can read or write
any fields of this RxBD. The CPM does not use this BD as long as the E bit is zero.
1 The buffer is not full. The CPM controls this BD and its buffer; do not modify this BD.
1 — Reserved, should be cleared.
2 W Wrap (final BD in table)
0 Not the last BD in the table
1 Last BD in the table. After this buffer is used, the CPM receives incoming data into the first BD
that RBASE points to. The number of BDs is determined only by the W bit.
3 I Interrupt. Note that this bit does not mask SCCE[RXF] interrupts.
0 No SCCE[RXB] interrupt is generated after this buffer is used.
1 SCCE[RXB] or SCCE[RXF] is set when this buffer is used by the ethernet controller. These two
bits can cause interrupts if they are enabled.
4 L Last in frame. The ethernet controller sets this bit when this buffer is the last one in a frame, which
occurs when the end of a frame is reached or an error is received. In the case of error, one or more
of the CL, OV, CR, SH, NO, and LG bits are set. The ethernet controller writes the number of frame
octets to the data length field.
0 The buffer is not the last one in a frame.
1 The buffer is the last one in a frame.
5 F First in frame. The ethernet controller sets this bit when this buffer is the first one in a frame.
0 The buffer is not the first one in a frame.
1 The buffer is the first one in a frame.
6 — Reserved, should be cleared.
7 M Miss. (valid only if L = 1) The ethernet controller sets M for frames that are accepted in promiscuous
mode, but are flagged as a miss by internal address recognition. Thus, in promiscuous mode, M
determines whether a frame is destined for this station.
0 The frame is received because of an address recognition hit.
1 The frame is received because of promiscuous mode.
8–9 — Reserved, should be cleared.
10 LG Rx frame length violation. Set when a frame length greater than the maximum defined for this
channel has been recognized. Only the maximum number of bytes allowed is written to the buffer.
11 NO Rx nonoctet-aligned frame. Set when a frame containing a number of bits not divisible by eight is
received. Also, the CRC check that occurs at the preceding byte boundary generated an error.
12 SH Short frame. Set if a frame smaller than the minimum defined for this channel was recognized.
Occurs if PSMR[RSH] = 1.
13 CR Rx CRC error. set when a frame contains a CRC error.
14 OV Overrun. Set when a receiver overrun occurs during frame reception.
15 CL Collision. This frame is closed because a collision occurred during frame reception. CL is set only if
a late collision occurs or if PSMR[RSH] is enabled. Late collisions are better defined in PSMR[LCW].
Data length and buffer pointer fields are described in
length includes the total number of frame octets (including four bytes for CRC).
Freescale Semiconductor
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Section 21.3, "SCC Buffer Descriptors (BDs)."
SCC Ethernet Mode
Data
27-17