Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 481

Bit Name
26–27 AMX Address multiplexing. Determines the source of A[0:31] at the falling edge of GCLK1_50.
00 A[0:31] is the non-multiplexed address. For example, column address.
01 Reserved.
10 A[0:31] is the address requested by the internal master multiplexed according to M x MR[AM x ].
For example, row address.
11 A[0:31] is the contents of MAR. Used for example, during SDRAM mode initialization.
28 NA Next address. Determines when the address is incremented during a burst access.
0 The address increment function is disabled
1 The address is incremented in the next cycle. With the BR x [PS], the increment value of A[28:31]
and/or BADDR[28:30] at the falling edge of GCLK1_50 is as follows
If the accessed bank has a 32-bit port size, the value is incremented by 4.
If the accessed bank has a 16-bit port size, the value is incremented by 2.
If the accessed bank has an 8-bit port size, the value is incremented by 1.
Note: The value of NA is relevant only when the UPM serves a burst-read or burst-write request.
NA is reserved under other patterns.
29 UTA UPM transfer acknowledge. Controls the state of TA sampled by the external bus interface in the
current memory cycle. TA is output at the rising edge of GCLK2_50.
0 TA is driven low on the rising edge of GCLK2_50. The bus master samples it low in the next clock
cycle.
1 TA is driven high on the rising edge of GCLK2_50.
30 TODT Turn-on disable timer. Controls the disable timer mechanism. This bit has meaning only in RAM
words for which UTA = 0; otherwise it is a don't care.
0 The disable timer is turned off.
1 The disable timer for the current bank is activated preventing a new access to the same bank
(when controlled by the UPMs) until the disable timer expires. For example, precharge time.
31 LAST Last. If this bit is set, it is the last RAM word in the program.
0 The UPM continues executing RAM words.
1 The service to the UPM request is done.
15.6.4.2 Chip-Select Signals (CST x )
If BRx[MS] of the accessed bank selects a UPM on the currently requested cycle the UPM manipulates
the CS signal for that bank with timing as specified in the UPM RAM word. The selected UPM affects
only assertion and negation of the appropriate CSx signal. The state of the selected CSx signal of the
corresponding bank depends on the value of each CSTn bit.
Figure 15-40 and the timing diagrams in
signals.
Freescale Semiconductor
Table 15-14. RAM Word Bit Settings (continued)
Figure 15-36
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
and Figure 15-37 shows how UPMs control CS
Memory Controller
15-41