Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 799

Dual-Port RAM
SMC TxBD
SMC RxBD
Pointer to SMCx
RxBD Table
Pointer to SMCx
TxBD Table
The BD table allows buffers to be defined for transmission and reception. Each table forms a circular
queue. The CP uses BDs to confirm reception and transmission so that the processor knows buffers have
been serviced. The data resides in external or internal buffers.
When SMCs are configured to operate in GCI mode, their memory structure is predefined to be one
half-word long for transmit and one half-word long for receive. For more information on these half-word
structures, see Section 29.5, "SMC in GCI Mode."
29.2.3 SMC Parameter RAM
Each SMC parameter RAM area begins at the same offset from each SMC base. The protocol-specific
portions of the SMC parameter RAM are discussed in the sections that follow. The SMC parameter RAM
shared by the UART and transparent protocols is shown in
is described in Section 29.5.1, "SMC GCI Parameter RAM."
Freescale Semiconductor
Status and Control
Table
Status and Control
Table
Figure 29-3. SMC Memory Structure
MPC885 PowerQUICC Family Reference Manual, Rev. 2
TxBD Table
Data Length
Buffer Pointer
RxBD Table
Data Length
Buffer Pointer
Table 29-2. Parameter RAM for GCI protocol
Serial Management Controllers (SMCs)
External Memory
Tx Data Buffer
Rx Data Buffer
29-5