Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 832

Serial Peripheral Interface (SPI)
• Master or slave SPI modes supported
• Multimaster environment support
• Continuous transfer mode for autoscanning of a peripheral
• Supports maximum clock rates of 6.25 MHz in master mode and12.5 MHz in slave mode,
assuming a 25-MHz system clock
• Independent programmable baud rate generator
• Programmable clock phase and polarity
• Open-drain outputs support multimaster configuration
• Local loopback capability for testing
30.2 SPI Clocking and Signal Functions
The SPI can be configured as a slave or as a master in single- or multiple-master environments. The master
SPI generates the transfer clock SPICLK using the SPI baud rate generator (BRG). The SPI BRG takes its
input from BRGCLK, which is generated in the MPC885 clock synthesizer.
SPICLK is a gated clock, active only during data transfers. Therefore, SPI clock rates can be very high, up
to BRGCLK/4 in master mode or BRGCLK/2 in slave mode. Note, however, that this high clock rate can
be supported only over the period of a single character, if messages consist of multiple back-to-back
characters, operation becomes limited by CPM performance, and thus the clock rate should be adjusted
down accordingly. CPM bandwidth required by the SPI channel should be calculated as the maximum rate
that back-to-back characters must be transmitted and received. Four combinations of SPICLK phase and
polarity can be configured with SPMODE[CI, CP]. SPI signals can also be configured as open-drain to
support a multimaster configuration in which a shared SPI signal is driven by the MPC885 or an external
SPI device.
The SPI master-in slave-out SPIMISO signal acts as an input for master devices and as an output for slave
devices. Conversely, the master-out slave-in SPIMOSI signal is an output for master devices and an input
for slave devices. The dual functionality of these signals allows the SPIs in a multimaster environment to
communicate with one another using a common hardware configuration.
• When the SPI is a master, SPICLK is the clock output signal that shifts received data in from
SPIMISO and transmitted data out to SPIMOSI. SPI masters must output a slave select signal to
enable SPI slave devices by using a separate general-purpose I/O signal. Assertion of an SPI's
SPISEL, while it is in master mode, causes an error.
• When the SPI is a slave, SPICLK is the clock input that shifts received data in from SPIMOSI and
transmitted data out through SPIMISO. SPISEL is the enable input to the SPI slave.
• In a multimaster environment, SPISEL (always an input) is also used to detect when more than one
master is operating, which is an error condition.
As described in Chapter 34, "Parallel I/O Ports,"
multiplexed with port B[28–31] signals, respectively. They are configured as SPI signals through the port
B signal assignment register (PBPAR) and the Port B data direction register (PBDIR), specifically by
setting PBPAR[DDn] and PBDIR[DRn].
30-2
SPIMISO, SPIMOSI, SPICLK, and SPISEL are
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor