Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 927

34.3.1 The Port B Registers
The four port B control registers determine whether a signal is open-drain, input or output, and
general-purpose or dedicated to a peripheral.
34.3.1.1 Port B Open-Drain Register (PBODR)
The port B open-drain register (PBODR) indicates when the port signals are configured in a normal or
wired-OR configuration. Bits 14 and 15 of PBODR are not implemented. PBODR is cleared by system
reset.
0
Field
Reset
R/W
Addr
16 17
Field OD16 OD17 OD18 OD19 0D20 0D21 OD22 OD23 OD24 OD25 OD26 OD27 OD28 OD29 OD30 OD31
Reset 0 0
R/W R/W R/W R/W
Addr
This register is affected by HRESET but is not affected by SRESET.
Bits Name
0–15 — Reserved
16–31 OD n Port B open-drain configuration.
0 The I/O signal is actively driven as an output.
1 The I/O signal is an open-drain driver. As an output, the signal is actively driven low. Otherwise,
it is three-stated.
Note: SMTXD1 cannot be configured as an open-drain driver, regardless of PBODR[OD25].
34.3.1.2 Port B Data Register (PBDAT)
Reading the port B data register (PBDAT) returns data to the signal, regardless of whether it is an input or
output. This allows output conflicts to be found on the signal by comparing the written data with the data
on the signal. Data written to PBDAT is latched; if the corresponding PBDIR bit is configured as an output,
the latched value is driven onto its respective signal. PBDAT can be read or written at any time and is not
initialized. This register is affected by HRESET and SRESET.
Freescale Semiconductor
0000_0000_0000_0000
18 19 20 21 22
0 0 0 0 0
R/W R/W R/W R/W
Figure 34-7. Port B Open-Drain Register (PBODR)
Table 34-7. PBODR Bit Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
—
—
0xAC0
23 24 25 26 27
0 0 0 0 0
R/W R/W R/W R/W R/W
0xAC2
Table 34-7
Description
Parallel I/O Ports
15
28 29 30 31
0 0 0 0
R/W R/W R/W R/W
describes PBODR bits.
34-9