Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 426

Clocks and Power Control
14.3.1.1 Internal General System Clocks
(GCLK1C, GCLK2C, GCLK1, GCLK2)
The GCLKxC and GCLKx signals are referred to here as GCLKx. The difference between the GCLKxC
and GCLKx signals are as follows:
• The GCLKxC clocks are supplied to the core, data and instruction caches, and memory
management unit.
• The GCLKx clocks are supplied to the SIU, clock module, memory controller, and most of the
other blocks in the CPM.
GCLKx can be dynamically switched between two different frequencies determined by dividers
programmed in SCCR[DFNH] and SCCR[DFNL], as shown in
divout1
The high frequency is generated by using the DFNH field in the SCCR, and it is used in normal high mode.
The low frequency is generated using the DFNL field in the SCCR, and it is used in normal low mode. The
DFNH and DFNL dividers are cleared by HRESET, and therefore GCLKx defaults to divout1, where
divout1 is equivalent to JDBCK divide by 2.
The frequency for the GCLKx system clock is:
When GCLKx is divided, its duty cycle is modified. One phase remains the same while the other stretches
out. GCLKx no longer has a 50% duty cycle when the division factor is greater than 1, as shown in
Figure 14-6.
14-10
DFNH Divider
DFNL Divider
Figure 14-5. Frequency Dividers for GCLK x
GCLKx freq = ------------------------------------------------------------------ -
DFNH
(
2
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Figure 14-5.
DFNH
2:1
MUX
DFNL
divout1 freq
DFNL + 1
)or 2 ( )
GCLK1
Freescale Semiconductor