Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 754

SCC BISYNC Mode
Table 26-14 describes SCCS fields.
Bit Name
0–5 — Reserved, should be cleared.
6 CS Carrier sense (DPLL). Shows the real-time carrier sense of the line as determined by the DPLL.
0 The DPLL does not sense a carrier.
1 The DPLL senses a carrier.
7 — Reserved, should be cleared.
26.16 Programming the SCC BISYNC Controller
Software has two ways to handle data received by the BISYNC controller. The simplest is to allocate
single-byte receive buffers, request an interrupt on reception of each buffer, and implement BISYNC
protocol entirely in software on a byte-by-byte basis. This flexible approach can be adapted to any
BISYNC implementation. The obvious penalty is the overhead caused by interrupts on each received
character.
A more efficient method is to prepare and link multi-byte buffers in the RxBD table and use software to
analyze the first two to three bytes of the buffer to determine the type of block received. When this is
determined, reception continues without further software intervention until it encounters a control
character, which signifies the end of the block and causes software to revert to byte-by-byte reception.
To accomplish this, set SCCM[RCH] to enable an interrupt on every received byte so software can analyze
each byte. After analyzing the initial characters of a block, either set PSMR[RTR] or issue a
command. For example, if a DLE-STX is received, enter transparent mode. By setting the
CALCULATION
appropriate PSMR bit, the controller strips the leading DLE from DLE-character sequences. Thus, control
characters are recognized only when they follow a DLE character. PSMR[RTR] should be cleared after a
DLE-ETX is received.
Alternatively, after an SOH is received, a
BCS accumulation and reset the BCS. Notice that PSMR[RBCS] is not needed because the controller
automatically excludes SYNCs and leading DLEs.
After the type of block is recognized, SCCE[RCH] should be masked. The core does not interrupt data
reception until the end of the current block, which is indicated by the reception of a control character
matching the one in the receive control character table. Using
should be set to recognize the end of the block.
ETX
ITB
ETB
ENQ
Next entry
26-16
Table 26-14. SCCS Field Descriptions
RESET BCS CALCULATION
Table 26-15. Control Characters
Control Characters
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
should be issued to exclude SOH from
Table 26-15, the control character table
E
0
0
0
0
0
RESET BCS
B H
1 1
1 0
1 1
0 0
X X
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