Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 442

Memory Controller
• General-purpose chip-select machine (GPCM)
— Compatible with SRAM, EPROM, FEPROM, and peripherals
— Global (boot) chip-select available at system reset
— Boot chip-select support for 8-, 16-, and 32-bit devices
— Minimum two clock accesses to external device
— Four byte write enable signals (WE)
— Output enable signal (OE)
• Two user-programmable machines
— Programmable-array-based machine controls external signal timing with a granularity of one
quarter of an external bus clock period
— User-specified control-signal patterns run when an internal or external synchronous master
requests a single-beat or burst read or write access.
— User-specified control-signal patterns run when an external asynchronous master requests a
single-beat read or write access.
— UPM periodic timer runs a user-specified control signal pattern to support refresh
— User-specified control-signal patterns can be initiated by software
— Each UPM can be defined to support DRAM devices with depths of 64, 128, 256, and 512
Kbytes, and 1, 2, 4, 8, 16, 32, 64, 128, and 256 Mbytes
— Each UPM provides programmable timing for the following signals:
– Four byte-select lines
– Six external general-purpose lines
— Supports 8-, 16-, and 32-bit DRAM port sizes
— Glueless interface to one bank of DRAM (only external buffers are required for additional
SIMM banks)
— Page mode support for successive transfers within a burst for all on-chip and external
synchronous devices
— Internal address multiplexing for all on-chip bus masters supporting 64-, 128-, 256-, and
512-Kbyte, and 1-, 2-, 4-, 8-, 16-, 32-, 64-, 128-, 256-Mbyte page banks
— Glueless interface to EDO, self refresh, and synchronous DRAM devices
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MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor