Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 906

Parallel Interface Port (PIP)
0
Field
Reset
R/W
Addr
Table 33-7 describes PIPE fields.
Bits Name
0–2 — Reserved, should be cleared.
3 TXE Transmit error. Indicates a general transmit error—the source of the specific error can be read in the
current buffer descriptor's status and control field; see
(TxBD)."
4 CCR Control character received. A control character was received and stored in the received control
character register (RCCR) in the PIP parameter RAM.
5 BSY Busy. Due to a lack of buffers, the PIP did not receive, and therefore discarded, a data
byte/half-word.
6 RCH/TCH Character received/transmitted. Indicates that a data character has been sent or received. Used to
generate interrupts to the core if the PIP is configured to be controlled by core software.
7 RXB/TXB Rx/Tx buffer. Under CP control, indicates that the PIP controller has closed the current buffer due to
one of the following events: the transfer byte count reaches zero (for Rx and Tx), a user-defined
control character is received and not rejected (R-bit = 0), or the programmable silence period times
out.
33.4.3 PIP Mask Register
The PIP mask register (PIPM), whose layout is identical to PIPE, shares address 0xA9A with the SMC2
mask register. Setting a PIPM bit enables the corresponding interrupt; clearing a bit disables the interrupt.
PIPM is cleared by reset.
33.4.4 PIP Timing Parameters Register (PTPR)
The PIP timing parameters register (PTPR) holds two timing parameters, TPAR1 and TPAR2, used in the
pulsed handshake modes for both sending and receiving. See
Timing."
33-10
2 3
TXE
—
Figure 33-6. PIP Event Register (PIPE)
Table 33-7. PIPE Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
4 5
CCR BSY
0
R/W
0xA96
Description
Section 33.5.1, "The PIP Tx Buffer Descriptor
Section 33.7.2.2, "Pulsed Handshake
6 7
RCH/TCH RXB/TXB
Freescale Semiconductor