Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 779

26. Initialize the TxBD and assume the Tx data frame is at 0x0000_2000 in main memory and contains
fourteen 8-bit characters (destination and source addresses plus the type field). Write 0xFC00 to
TxBD[Status and Control], add PAD to the frame and generate a CRC. Then write 0x000E to
TxBD[Data Length] and 0x0000_2000 to TxBD[Buffer Pointer].
27. Write 0xFFFF to the SCCE register to clear any previous events.
28. Write 0x001A to the SCCM register to enable the TXE, RXF, and TXB interrupts.
29. Write 0x8000_0000 to the CIMR so that SCC2 can generate a system interrupt. The CICR register
should also be initialized.
30. Write 0x0000_0000 to GSMR_H2 to enable normal operation of all modes.
31. Write 0x1088_000C to the GSMR_L2 register to configure CTS (CLSN) and CD (RENA) to
automatically control transmission and reception (DIAG bits) and the ethernet mode. TCI is set to
allow more setup time for the EEST to receive the MPC885 transmit data. TPL and TPP are set for
ethernet requirements. The DPLL is not used with ethernet. Note that the ENT and ENR are not
enabled yet.
32. Write 0xD555 to the DSR.
33. Set the PSMR2 to 0x0A0A to configure 32-bit CRC, promiscuous mode, and begin searching for
the start frame delimiter 22 bits after RENA.
34. Enable the TENA pin (RTS). Since GSMR[MODE] are written to ethernet, the TENA signal is
low. Set PCPAR[14] and clear PCDIR[14].
35. Write 0x1088_003C to GSMR_L2 to enable the SCC2 transmitter and receiver. This additional
write ensures that ENT and ENR are enabled last.
After 14 bytes and the 46 bytes of automatic pad (plus the 4 bytes of CRC) are sent, the TxBD is closed.
Additionally, the receive buffer is closed after a frame is received. Any data received after 1520 bytes or
a single frame causes a busy (out-of-buffers) condition because only one RxBD is prepared.
Freescale Semiconductor
MPC885 PowerQUICC Family Reference Manual, Rev. 2
SCC Ethernet Mode
27-23