Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 924

Parallel I/O Ports
• PA11 can be configured as a general-purpose I/O and an open-drain signal. It can also be the
MII1-TXD0 or RMII1-TXD0 if PADIR[DR11] is a 1.
• PA7 can be configured as a general-purpose I/O signal but not an open-drain signal.
— If PADIR[DR7] = 0, PA7 can also be CLK1, TIN1, L1RCLKA, or all three. The connections
are made separately in the serial interface and timer mode registers.
— If PADIR[DR7] = 1, PA7 can also be BRGO1. If PA7 is a general-purpose I/O signal, the input
to the on-chip peripheral is connected internally to BRG01.
describes CLK1 and L1RCLKA.
• PA4 can be configured as a general-purpose I/O signal but not an open-drain signal.
— If PADIR[DR4] = 0, PA4 can be CTS4. If DR4 = 1, PA4 can be MII1-TXD1 or RMII1-TXD1.
— If PA4 is a general-purpose I/O signal, the CTS4 can be input from PC7.
34.2.3 Port A Functional Block Diagrams
Using PA15 as an example,
open-drain capability.
Read Path To
PADAT[15]
Write Path
From
RXD1
To SCC1
Figure 34-5. Block Diagram for PA15 (True for all Non-Open-Drain Port Signals)
Using PA14 as an example,
open-drain capability.
34-6
Figure 34-5 shows the functional block diagram for all port A signals without
EN
Output
Latch
16-Bits
PADIR
0
MUX
1
EN
Figure 34-6 shows the functional block diagram for all port A signals with
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Chapter 20, "Serial Interface,"
0 0
MUX MUX
1 1
EN EN
EN
16-Bits
PAPAR
RXD1/PA15
Pin
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