Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 968

Powerquicc family

Table of Contents

ATM Overview

Overview of ATM Operation

The MPC885 supports ATM adaptation layers AAL0 and AAL5 segmentation and reassembly (SAR), and

the ATM layer for the convergence sub-layer (CS). User data resides in system memory in single or

multiple data buffers.

There are two physical layer/interface modes of operation: a UTOPIA interface and a serial interface. In

UTOPIA mode, the ATM layer directly interfaces to the PHY through the UTOPIA interface. In serial

mode, the ATM controller also implements the transmission convergence (TC) sublayer and interfaces to

the PHY layer through the SCCs.

The following sections describe the transfer mechanisms for the serial and UTOPIA interface modes and

the functionality of the ATM pace controller (APC), which is utilized in both modes of operations. Internal

and external ATM channels are introduced. Port-to-port cell switching and memory-to-memory SAR

operation is also discussed.

UTOPIA Operation

In UTOPIA mode, the ATM controller handles transfers on a cell-by-cell basis. The UTOPIA interface

implements a cell-level handshake. The supported bit rate of the UTOPIA interface is higher than that of

serial ATM which additionally implements the transmission convergence (TC) layer.

Communications

Figure 36-1. MPC885 Application Example

MPC885 PowerQUICC Family Reference Manual, Rev. 2

DRAM / EPROM / SRAM

Freescale Semiconductor