Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 224

Instruction and Data Caches
Table 7-7 describes the bits of the DC_CST register.
Table 7-7. Data Cache Control and Status Register—DC_CST
Bits Name
0 DEN Data cache enable status
0 The data cache is disabled.
1 The data cache is enabled.
Note: This is a read-only bit. Any attempt to write to it is ignored. This bit is programmed by issuing
1 DFWT Data cache forced write-through
0 The write-through behavior of the data cache is determined by the write-through memory/cache
access attribute (the W bit) in the MMU.
1 Writes to the data cache are forced to write through to memory.
Note: This is a read-only bit. Any attempt to write to it is ignored. This bit is programmed by issuing
2 LES Little-endian swap
0 Used for big-endian (BE) and modified little-endian (MOD-LE) modes. No modifications to the
address or byte lanes are performed.
1 Used for true little-endian (TLE) mode. A 2-bit munge is performed on the physical address before
accessing the internal U-bus. Also, for accesses originating from the MPC8xx core, the SIU
unmunges the address and swaps the bytes of data within each word at the external bus/internal
U-bus boundary.
See Appendix A, "Byte Ordering,"
is a read-only bit. Any attempt to write to it is ignored. This bit is programmed by issuing the
appropriate command in DC_CST[CMD].
3 Reserved
4–7 CMD Data cache command
0000 Reserved
0001 Set forced write-through bit
0010 Cache enable
0011 Clear forced write-through bit
0100 Cache disable
0101 Set true little-endian swap bit
0110 load-and-lock cache block
0111 Clear little-endian swap bit
1000 Unlock cache block
1001 Reserved
1010 Unlock all
1011 Reserved
1100 Invalidate all
1101 Reserved
1110 Flush cache block
1111 Reserved
Note: Reading these bits always returns 0b0000
8–9 Reserved
10 CCER1 Data cache error type 1. Copyback error during dcbf or dcbst instruction execution or during
DC_CST flush cache block command. A machine check exception is generated when this bit is set.
0 No error detected
1 Error detected
Note that this is a read-only, sticky bit, set only by the MPC885 when an error is detected. Reading
this bit clears it.
7-12
the appropriate command in DC_CST[CMD].
the appropriate command in DC_CST[CMD].
for more information about MPC885 byte ordering. Note that this
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Freescale Semiconductor