Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 346

External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Hard
Name
Reset
PB[26] Hi-Z
I2CSCL
BRGO2
PB[25] Hi-Z
SMTXD1
RXADDR3
TXADDR3
PB[24] Hi-Z
SMRXD1
TXADDR3
RXADDR3
PB[23] Hi-Z
SMSYN1
SDACK1
TXADDR2
RXADDR2
PB[22] Hi-Z
SMSYN2
SDACK2
TXADDR3
RXADDR3
PB[21] Hi-Z
SMTXD2
BRGO1
PHSEL[1]
TXADDR1
RXADDR1
PB[20] Hi-Z
SMRXD2
L1CLKOA
PHSEL[0]
TXADDR0
RXADDR0
12-16
Number Type
R17 Bidirectional General-Purpose I/O Port B Bit 26—Bit 26 of the general-purpose
(optional: I/O port B
open-drain) I2CSCL—I
as an open-drain output
BRGO2—BRG2 output clock
V17 Bidirectional General-Purpose I/O Port B Bit 25—Bit 25 of the general-purpose
(optional: I/O port B
open-drain) SMTXD1—SMC1 transmit data output
UTOPIA multi-PHY receive address line 3 - only if in ESAR mode
UTOPIA multi-PHY transmit address line 3
U16 Bidirectional General-Purpose I/O Port B Bit 24—Bit 24 of the general-purpose
(optional: I/O port B
open-drain) SMRXD1—SMC1 receive data input
UTOPIA multi-PHY transmit address line 3 - only if in ESAR mode
UTOIPIA multi-PHY receive address line 3
W16 Bidirectional General-Purpose I/O Port B Bit 23—Bit 23 of the general-purpose
(optional: I/O port B
open-drain) SMSYN1—SMC1 external sync input
SDACK1—SDMA acknowledge 1 output that is used as a
peripheral interface signal for IDMA emulation, or as a CAM
interface signal for Ethernet
UTOPIA multi-PHY transmit address line 2 - only if in ESAR mode
UTOPIA multi-PHY receive address line 2
V15 Bidirectional General-Purpose I/O Port B Bit 22—Bit 22 of the general-purpose
(optional: I/O port B
open-drain) SMSYN2—SMC2 external sync input
SDACK2—SDMA acknowledge 2 output that is used as a
peripheral interface signal for IDMA emulation
UTOPIA multi-PHY transmit address line 4 - only if in ESAR mode
UTOPIA multi-PHY receive address line 4
U14 Bidirectional General-Purpose I/O Port B Bit 21—Bit 21 of the general-purpose
(optional: I/O port B
open-drain) SMTXD2—SMC2 transmit data output
BRGO1—Output clock of BRG1
PHSEL[1]—Least-significant bit of PHY select bus (used in
classic SAR MPHY mode only)
UTOPIA multi-PHY transmit address line 1 - only if in ESAR mode
UTOPIA multi-PHY receive address line 1
T13 Bidirectional General-Purpose I/O Port B Bit 20—Bit 20 of the general-purpose
(optional: I/O port B
open-drain) SMRXD2—SMC2 receive data input
L1CLKOA—Clock output from the serial interface TDMa
PHSEL[0]—Most significant bit of PHY select bus (used in classic
SAR MPHY mode only)
UTOPIA multi-PHY transmit address line 0 - only if in ESAR mode
UTOPIA multi-PHY receive address line 0
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
2
C serial clock pin. Bidirectional; should be configured
Freescale Semiconductor