Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 45

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Number
53.3.2.1.3 Development Serial Data Out (DSDO) ........................................................... 53-24
53.3.2.1.4 Freeze............................................................................................................... 53-25
53.3.2.2 Development Port Registers ................................................................................ 53-25
53.3.2.2.1 Development Port Shift Register ..................................................................... 53-25
53.3.2.2.2 Trap Enable Control Register (TECR) ............................................................ 53-25
53.3.2.2.3 Development Port Registers Decode ............................................................... 53-26
53.3.2.3 Development Port Serial Communications–Clock Mode.................................... 53-26
53.3.2.3.1 Asynchronous Clocked Mode—Using DSCK ................................................ 53-26
53.3.2.3.2 Synchronous Self-Clocked Mode—Using CLKOUT ..................................... 53-27
53.3.2.3.3 Selection of Development Port Clock Mode ................................................... 53-27
53.3.2.4 Development Port Serial Communications–Trap Enable Mode.......................... 53-28
53.3.2.4.1 Serial Data Into Development Port.................................................................. 53-28
53.3.2.4.2 Serial Data Out of Development Port.............................................................. 53-29
53.3.2.5 Development Port Serial Communications–Debug Mode .................................. 53-30
53.3.2.5.1 Serial Data Into Development Port.................................................................. 53-30
53.3.2.5.2 Serial Data Out of Development Port.............................................................. 53-31
53.3.2.5.3 Fast Download Procedure................................................................................ 53-32
53.4 Software Monitor Debugger Support .......................................................................... 53-33
53.4.1 Freeze Indication...................................................................................................... 53-33
53.5 Development Support Programming Model................................................................ 53-33
53.5.1 Development Support Registers .............................................................................. 53-35
53.5.1.1 Comparator A–H Value Registers (CMPA–CMPH) ........................................... 53-35
53.5.1.2 Breakpoint Address Register (BAR) ................................................................... 53-36
53.5.1.3 Instruction Support Control Register (ICTRL).................................................... 53-37
53.5.1.4 Load/Store Support Comparators Control Register (LCTRL1) .......................... 53-38
53.5.1.5 Load/Store Support AND-OR Control Register (LCTRL2)................................ 53-40
53.5.1.6 Breakpoint Counter Value and Control
Registers (COUNTA/COUNTB)..................................................................... 53-42
53.5.2 Debug Mode Registers............................................................................................. 53-42
53.5.2.1 Interrupt Cause Register (ICR)............................................................................ 53-42
53.5.2.2 Debug Enable Register (DER)............................................................................. 53-44
53.5.2.3 Development Port Data Register (DPDR) ........................................................... 53-46
54.1 Overview........................................................................................................................ 54-1
54.2 TAP Controller............................................................................................................... 54-2
54.3 Boundary Scan Register................................................................................................. 54-3
54.4 Instruction Register........................................................................................................ 54-5
54.4.1 EXTEST..................................................................................................................... 54-6
Freescale Semiconductor
Contents
Title
Chapter 54
IEEE 1149.1 Test Access Port
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
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