Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 715

wired-OR scheme, a transmitted zero has priority over a transmitted 1.
used to detect collisions.
TCLK
TXD
(Output)
CTS
(Input)
If both the destination address and source address are included in the HDLC frame, then a predefined
priority of stations results; if two stations begin to transmit simultaneously, they necessarily detect a
collision no later than the end of the source address.
The HDLC bus priority mechanism ensures that stations share the bus equally. To minimize idle time
between messages, a station normally waits for eight one bits on the line before attempting transmission.
After successfully sending a frame, a station waits for 10 rather than eight consecutive one bits before
attempting another transmission. This mechanism ensures that another station waiting to transmit acquires
the bus before a station can transmit twice. When a low priority station detects 10 consecutive ones, it tries
to transmit; if it fails, it reinstates the high priority of waiting for only eight ones.
23.14.3 Increasing Performance
Because it uses a wired-OR configuration, HDLC bus performance is limited by the rise time of the one
bit. To increase performance, give the one bit more rise time by using a clock that is low longer than it is
high, as shown in Figure
TCLK
TXD
(Output)
CTS
(Input)
Figure 23-13. Nonsymmetrical Tx Clock Duty Cycle for Increased Performance
Freescale Semiconductor
CTS sampled at halfway point.
Collision detected when
TXD=1, but CTS=0.
Figure 23-12. Detecting an HDLC Bus Collision
23-13.
CTS sampled at three quarter point.
Collision detected when
TXD=1, but CTS=0.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
SCC HDLC Mode
Figure 23-12 shows how CTS is
23-19